כאן תמצאו את ג׳וב החלומות שלכם

lectrical Engineering Science degree (B.Sc.)
· At least 5 years hands-on experience with FPGA design
· Knowledge in SystemVerilog RTL coding
· Familiar with scripts languages – Perl / Bash / Python / TCL
· High motivation, be self-driven and be able to work as a Team player and also perform independent tasks